The present invention relates to a semiconductor device having a capacitor and a method of manufacturing the same.
In recent years, proposed is a semiconductor device using a Cu wiring of a damascene structure in accordance with progress in the fineness of the element.
FIG. 16 is a cross sectional view showing a conventional semiconductor device of a damascene structure. As shown in the drawing, a first wiring 62 made of, for example, Cu is formed in a SiO2 film 61, and a dielectric film 63 is formed on the first wiring 62. Further, an upper electrode 64 is formed on the dielectric film 63. Still further, a via hole 66 connected to the upper electrode 64 is formed in an interlayer insulating film 65, and a second wiring 67 made of, for example, Cu, which is connected to the via hole 66, is formed on the interlayer insulating film 65.
In the conventional semiconductor device of the construction described above, the first wiring 62, the dielectric film 63 and the upper electrode 64 collectively form a capacitor 68. In other words, the first wiring 62 buried in the SiO2 film 61 plays the role of the lower electrode of the capacitor 68. The first wiring 62 is hereinafter referred to as a lower electrode.
However, in the conventional semiconductor device of the construction described above, the capacitance of the capacitor 68 is determined by the surface area of any of the lower electrode 62 and the upper electrode 64 having a smaller surface area. Therefore, where a capacitor having a large capacitance is required, it is necessary to enlarge the surface area of not only the upper electrode 64 but also the lower electrode 62. Such being the situation, it was very difficult to form a capacitor having a large capacitance while promoting the fineness of the element.
FIG. 17 shows in a magnified fashion the portion B shown in FIG. 16. As shown in FIG. 17, an edge portion 64a of the upper electrode 64 on the side of the dielectric film 63 forms an acute angle, with the result that the electric field is concentrated on the edge portion 64a, giving rise to a problem that the reliability of the element is lowered.
Further, although many of the capacitors used as analog passive elements are capacitors fixed at one kind of capacitance, there is a case where it is required to form within a single layer a plurality of capacitors having various capacitance values. For example, in order to cope with the pairing problem of the capacitors which occur nonuniform capacitance values that the capacitance values are rendered nonuniform among the capacitors, it is considered effective to diminish the influence given by the nonuniform capacitance values. However, if the area of the capacitor is increased, the delay time accompanying the charging is rendered long, making it necessary to diminish the capacitance per unit area of the capacitor because the capacitor having a small capacitance permits shortening the charging time so as to shorten the delay time accompanying the charging. For meeting such demands, it has become necessary to form a plurality of capacitors having at least two kinds of capacitance values within a single layer without increasing the chip area.
As described above, it was very difficult in the conventional semiconductor device to form a plurality of capacitors having a large capacitance or at least two kinds of capacitance values while promoting the fineness of the element. An additional problem to be noted is that an electric field is concentrated in an edge portion of the electrode so as to lower the reliability of the element.